1. Field of the Invention
The present disclosure is generally directed to the field of semiconductor processing, and, more particularly, to a method of forming metal gate structures and metal contacts in a common fill process.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, etc. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, the size of many components of a typical field effect transistor, e.g., channel length, source/drain junction depths, gate dielectric thickness, etc., are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
By way of background, many semiconductor devices, e.g., transistors, may be manufactured using either a “gate-first” technique or a “gate-last” technique. The techniques selected depends upon many factors, such as the type of device under construction, the desired performance characteristics, etc. As it relates to transistors, in a typical “gate-first” approach, the final gate electrode structure is formed earlier in the process as compared to when the final gate electrode is formed in a typical “gate-last” approach. More specifically, in a “gate-first” approach, the gate material is deposited on a previously formed gate insulation layer, and thereafter an etching process is performed to define the final gate electrode. Processing continues with the formation of other related structure, e.g., source/drain regions, sidewall spacers, silicide regions, etc., with the final gate electrode in place In the “gate-first” technique, the final gate electrode must be made of a material that is able to withstand all of the subsequent processing operations, e.g., various heat treatments, etc. For that reason, use of the “gate-first” technique tends to limit the material that may be used for the gate electrode. In contrast, in the “gate-last” technique, a “dummy gate” material is formed early in the process and serves as a placeholder for what will ultimately be the final gate electrode structure. At some point after other aspects of the transistor have been formed, e.g., after the source/drain regions, the sidewall spacers, etc. have been formed, the dummy gate material will be removed and a replacement gate electrode material will be formed in its place. This replacement gate electrode is the final gate electrode for the transistor. Since the replacement gate electrode material is not subject to all of the processing conditions that the gate electrode in a “gate-first” technique is subjected to, the final gate electrode in a “gate-last” technique may be made of a variety of different metals or other conductive material. Thus, the “gate-last” technique gives designers more flexibility as to the final gate electrode material which can be important in the ultimate performance of the device.
In a typical “gate-last” approach, the contacts to the active area are formed at a different time than when the replacement gate electrode is formed. One problem with this typical technique is that it involves multiple deposition and chemical mechanical polishing (“CMP”) steps. Among other things, CMP steps tend to create defects, such as microscratches, slurry defects, and the like, all of which tend to reduce product yields.
The present invention is directed to solving, or at least reducing, some or all of the aforementioned problems.